Thin film fabrication of capacitors has become an important technology, particularly in dynamic random access memories (DRAMs), as die size of many semiconductor devices continue to shrink.
In DRAMs, the storage capacitor has taken on many innovative designs and encompasses many materials, all for the sake of reducing the die space required for a given capacitor while maintaining or even increasing the storage capability of a capacitor.
As DRAM density has increased (1 MEG and beyond) thin film capacitors, such as stacked capacitors, trenched capacitors, or combinations thereof, have evolved in attempts to meet minimum space requirements. Many of these designs have become elaborate and difficult to fabricate consistently as well as efficiently.
The recent generations of DRAMs (4 MEG, 16 MEG for example) have pushed thin film capacitors technology to the limit of processing capability thus, greater attention has been given to the development of thin film dielectric materials that possess a dielectric constant having at least a 10X increase over the conventional dielectrics used today (oxides and nitrides).
Recently, a lot of attention has been paid to Barium Strontium Titanate Strontium Titanate (ST), Barium Titanate (BT), Lead Zirconate Titanate (PZT) and other high dielectric constant materials as a cell dielectric material of choice for DRAMs. These materials and in particular BST, have a high dielectric constant (&gt;300) and low leakage currents which makes them very attractive for high density memory chips. These materials, however, suffer from many drawbacks. One major hurdle to incorporating these material into present day design is the fact that they react with polysilicon.
Capacitors made by polysilicon-PZT/BST sandwiches undergo physical degradation with thermal cycles. During chemical vapor deposition (CVD) of PZT/BST, oxygen in the ambient tends to oxidize the electrode material. This however, is undesirable since oxide has a much lower dielectric constant compared to PZT/BST and adds to the capacitance in series thus drastically lowering the total capacitance of the capacitor. Therefore, even a thin native layer of oxide grown on the electrode results in a large degradation in capacitance.
Solutions to the problem which include triple layer cell plates consisting of poly Si/Ta/Pt as disclosed in "A STACKED CAPACITOR WITH (BaxSr1-x)TiO3 for 256M DRAM", K. Koyama et al., IEDM 91, pp 823-826, and U.S. Pat. No. 5,053,917, Miyasaka et al., are complex and cumbersome to put into a manufacturing process flow (also see FIG. 1 of this disclosure).
The simpler cell plate scheme of the present invention will address all the issues mentioned above and thereby provide a manufacturable capacitor for future DRAM generations.
All U.S. Patents and publications cited herein are hereby incorporated by reference.